Product Overview
4-Mbit In-System Programmable Configuration PROM for Xilinx FPGAs, JTAG Programmed, 3.3 V Core
Condition
Condition: unused, new old stock (NOS). Sold each.
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Product Overview
An SRAM-based FPGA loses its configuration at every power-down, and a configuration PROM hands it back at power-up. The XC18V04 is the 4-Mbit member of Xilinx's XC18V00 in-system-programmable family, reprogrammed in circuit through its JTAG port instead of being pulled for a device programmer.
Key Features
- Part number: XC18V04 (Xilinx XC18V00 series)
- Density: 4,194,304 configuration bits (4 Mbit)
- Programming: in-system, through the IEEE 1149.1 boundary-scan (JTAG) port
- Core supply (VCCINT): 3.3 V, 3.0 V to 3.6 V range
- Configuration: serial slow or fast up to 33 MHz; parallel up to 264 Mb/s at 33 MHz
- Endurance: 20,000 program/erase cycles
- Data retention: 20 years
- Package: 44-lead quad package
Applications
- Replacing the configuration PROM on a legacy board designed around an XC18V04
- Stocking spares for a repair bench that services Xilinx FPGA boards of the XC18V00 era
- Holding the bitstream for a hobby FPGA build so it boots with no PC attached
Frequently Asked Questions
How is the XC18V04 programmed?
In the system, through its IEEE 1149.1 boundary-scan (JTAG) port. A JTAG programmer loads the bitstream with the chip in place on the board.
What supply voltage does it need?
A 3.3 V core supply. The XC18V00 series core runs from 3.0 V to 3.6 V.
An SRAM FPGA wakes up blank every time and waits for a PROM like this one to tell it what to be. What the PROM says gets written through its JTAG port, by whoever holds the cable.
